1. Technical Field
The present invention is concerned with so-called xe2x80x9ccontrolled collapse chip connectionxe2x80x9d or C4 semiconductor devices that employ solder bump interconnections, also known as flip chip or face down bonding. Specifically, the present invention relates to assembling, such devices, together with surface mount technology (SMT) devices, on a single carrier surface while allowing convenient dicing, subsequent processing, and preparation for surface mount assembly on cards and boards.
2. Background of Invention
Controlled collapse chip connection technology has been successfully used for decades to interconnect high input/ouput (I/O) count and area array solder bumps on integrated circuit chips to the base ceramic e.g. alumina, carriers. See U.S. Pat. No. 5,668,059 to Christie et al. and assigned to the assignee of the present patent application, disclosure of which is incorporated herein by reference, for further discussion of the C4 interconnection technology.
The rapidly increasing sophistication of integrated circuit devices has resulted in greatly increased chip sizes, but of even more significance, in explosively larger numbers of I/O terminals that must be solder connected. The advantage of solder joining is that the I/O terminals may be distributed over substantially the entire top surface of the semiconductor device. This efficient use of the entire surface area is known as area array bonding
The usual practice involves mounting the integrated circuit semiconductor device, normally formed of monocrystalline silicon having a coefficient of thermal expansion 2.5xc3x9710xe2x88x926 per xc2x0 C., on a substrate, either alumina (5.8xc3x9710xe2x88x926 per xc2x0 C.) or a rigid or flexible organic material (coefficient of thermal expansion ranging from 6xc3x9710xe2x88x926 per xc2x0 C. to 24xc3x9710xe2x88x926 per xc2x0 C.). The active and passive circuit elements generate heat that is conducted through the electrical connections. As a result the devices and their carriers expand and contract differentially imposing stresses on the relatively rigid solder joints. The stress on the solder joints is inversely proportional to the height of the solder bump, but the larger the number of I/O terminals incorporated into the device, the smaller the individual solder bumps become.
To provide mechanical stability and electrical isolation, Beckham et al. disclose in U.S. Pat. No. 4,604,644 (assigned to assignee of present invention and disclosure of which is hereby incorporated by reference) an improved solder interconnection structure with increased fatigue life. In particular their method for electrically joining a semiconductor device to a support substrate that has a plurality of solder connections incorporates a dielectric, organic material disposed between the semiconductor device and the supporting substrate to provide both electrical isolation and mechanical stability.
U.S. Pat. No. 5,668,059 to Christie et al. and assigned to the assignee of the present application, disclosure of which is hereby incorporated by reference, discloses an improved organic encapsulating adhesive formulation.
During the process of manufacturing semiconductor devices a plurality of dies, each containing an integrated circuit, are fabricated on a semiconductor wafer. Saw kerf lines are provided between adjacent dies such that the wafer may be sliced with a diamond saw into individual chips. Subsequent to the slicing operation, each individual chip is provided with an array of solder bumps to facilitate electrical connection With the chip carrier to which it will ultimately be mated. And in separate steps. the individual chips are coated with an adhesive formulation to provide stable, mechanical bonding between the chip and its carrier and a flux application is made to enable flow of the solder bumps during subsequent heating steps. The individual encapsulated chips are packaged to await placement on camers.
Mixtutes of adhesive and flux which can be applied to chips in a single step are now in development at Dexter Corporation, Windsor Locks, CT. Clearly, great reductions in processing time could be realized if such flux-adhesive formulation could be applied to the plurality of dies in a single step instead of having to be applied to individual chips. However, currently, a disadvantage of attempting such wafer-scale application is that the flux-adhesive formulations aggregate to and disable the diamond saw used to slice the wafer.
The present invention addresses problems encountered in attempting to apply adhesive and flux compositions to a plurality of dies at the same time. The present invention relates to a device and process for applying mixtures of such formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps.
The present invention provides a method by which the flux-adhesive formulation is screened onto the wafer using a stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Moreover, the invention provides a means of forming a dam about the peripheral area of the wafer, thus preventing the formulation from contaminating the edge of the wafer or from escaping from the surface of the wafer. The present invention also permits greater production throughput by permitting the application of combined flux-adhesive formulations, in a single step, to a plurality of chips, rather than requiring a separate step for each chip.
The present invention provides a means by which both flip-chip and SMT devices may be placed on a single surface of a carrier and reflowed in a single step.
In particular, the present invention is concerned with a screening mask for screening of a formulation for mounting a combination of flip chip and SMT devices on a carrier comprising peripheral members;
a lattice of kerf protecting members disposed to cover the saw kerf area of the corresponding semiconductor chip and connected to the peripheral members,
membrane of mask material 25 interconnecting the lattice of kerf protecting members, the membrane having a pattern of openings.
Another aspect of the present invention is concerned with a method of using a screening head above the disclosed screening mask. The method comprises aligning the screening mask over a semiconductor wafer;
aligning an extrusion head over the screening mask with wiping blades contacting the screening mask;
extruding an encapsulant flux mixture; and
traversing the extrusion head thereby removing excess encapsulant flux mixture.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.